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RFP30N06LE, RF1S30N06LESM
Data Sheet January 2004
30A, 60V, ESD Rated, 0.047 Ohm, Logic Level N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. These transistors incorporate ESD protection and are designed to withstand 2kV (Human Body Model) of ESD. Formerly developmental type TA49027.
Features
* 30A, 60V * rDS(ON) = 0.047 * 2kV ESD Protected * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER RFP30N06LE RF1S30N06LESM PACKAGE TO-220AB TO-263AB BRAND P30N06LE 1S30N06L
G
NOTE: When ordering use the entire part number. Add suffix, 9A, to obtain the TO-263 variant in tape and reel i.e. RF1S30N06LESM9A.
S
Packaging
JEDEC TO-220AB JEDEC TO-263AB
SOURCE DRAIN GATE DRAIN (FLANGE)
GATE SOURCE
DRAIN (FLANGE)
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified RFP30N06LE, RF1S30N06LESM 60 60 +10, -8 30 Refer to Peak Current Curve Refer to UIS Curve 96 0.645 2 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (R GS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrostatic Discharge Rating, MIL-STD-883, Category B(2). . . . . . . . . . . . . . . .ESD Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC kV oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, V GS = 0V, Figure 11 VGS = VDS, ID = 250A, Figure 10 VDS = Rated BVDSS , VGS = 0 VDS = 0.8 x Rated B VDSS, VGS = 0, TC = 150oC MIN 60 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDS = 25V, VGS = 0V, f = 1MHz Figure 12 VDD = 48V, ID = 30A, RL = 1.6 Figures 18, 19 TYP 11 88 30 40 51 28 1.8 1350 290 85 MAX 2 25 250 10 0.047 140 100 62 34 2.6 1.55 80 UNITS V V A A A ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero Gate Voltage Drain Current
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJC RJA
VGS = +10, -8V ID = 30A, VGS = 5V, Figure 9 VDD = 30V, ID = 30A, RL = 1, VGS = 5V, RGS = 2.5, Figures 13, 16, 17
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr ISD = 30A ISD = 30A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER
Unless Otherwise Specified
40
1.0 ID , DRAIN CURRENT (A) 30 0.8 0.6 0.4 0.2 0 25
20
10
0 0 25
125 50 75 100 TC , CASE TEMPERATURE (oC)
150
175
50
75
100
125
150
175
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
1 0.5 ZJC , NORMALIZED THERMAL IMPEDANCE 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 10-5 10 -4 10-3 10 -2 t, RECTANGULAR PULSE DURATION (s) 10-1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10 0 101 PDM
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200 100 ID , DRAIN CURRENT (A)
TJ = MAX RATED
IDM , PEAK CURRENT CAPABILITY (A)
TC = 25 oC
500 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - T c I = I ---------------------- 25 150
100ms
VGS = 10V 100
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
1ms 10ms 100ms DC
VGS = 5V TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 20 10-6 10-5 10-4 10-3 10-2 10 -1 t, PULSE WIDTH (s)
TC = 25oC
1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100
10 0
101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM Typical Performance Curves
100 100 IAS , AVALANCHE CURRENT (A) STARTING TJ = 25oC STARTING TJ = 150oC ID , DRAIN CURRENT (A) 80 TC = 25oC VGS = 10V VGS = 5V VGS = 4.5V 60 VGS = 4V 40 VGS = 3V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 10 0 0 1.5 4.5 3.0 6.0 VDS , DRAIN TO SOURCE VOLTAGE (V) 7.5
Unless Otherwise Specified (Continued)
10
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.01 1 0.1 tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON) , DRAIN TO SOURCE CURRENT (A)
100 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. 80 -55oC 25 oC 175oC
3.0 2.5 2.0 1.5 1.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX. VGS = 5V, I D = 30A
60
40
20 VDD = 15V 0 0 6.0 1.5 3.0 4.5 VGS , GATE TO SOURCE VOLTAGE (V) 7.5
0.5 0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, I D = 250A
2.0 ID = 250A 1.5
NORMALIZED GATE THRESHOLD VOLTAGE
1.5
1.0
1.0
0.5
0.5
0 -80
-40
160 120 0 40 80 TJ , JUNCTION TEMPERATURE (oC)
200
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM Typical Performance Curves
2000
Unless Otherwise Specified (Continued)
VDS , DRAIN TO SOURCE VOLTAGE (V) 5.0 VDD = BVDSS 45 VDD = BVDSS 3.75
C, CAPACITANCE (pF)
1500
CISS
1000
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD COSS CRSS
30
2.5 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS RL = 2.0 IG(REF) = 0.62mA VGS = 5V IG(REF) IG(ACT) IG(REF) IG(ACT)
15
1.25
500
0 20 t, TIME (s) 80
0
0 0
10 15 20 5 VDS , DRAIN TO SOURCE VOLTAGE (V)
25
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) RL VDS VGS VGS
+
tOFF td(OFF) tr tf 90%
VDS
90%
0V RGS DUT
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
VGS , GATE TO SOURCE VOLTAGE (V)
60
RFP30N06LE, RF1S30N06LESM Test Circuits and Waveforms
VDS RL VDD VDS VGS = 10V VGS
+
(Continued)
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IG(REF) 0 VGS = 5V
DUT IG(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
RFP30N06LE, RF1S30N06LESM PSPICE Electrical Model
SUBCKT RFP30N06LE 2 1 3; CA 12 8 1 3.34e-9 CB 15 14 3.44e-9 CIN 6 8 0 1.343e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DESD1 91 9 DESD1MOD DESD2 91 7 DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 75.39 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 7.22e-9 LSOURCE 3 7 6.31e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 11.86e-3 RGATE 9 20 2.52 RIN 6 8 1e9 RSCL1 5 51 RSLVCMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 26.6e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.5 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/89,7)) .MODEL DBDMOD D (IS = 3.80e-13 RS = 1.12e-2 TRS1 = 1.61e-3 TRS2 = 6.08e-6 CJO = 1.05e-9 TT = 3.84e-8) .MODEL DBKMOD D (RS = 1.82e-1 TRS1 = 7.50e-3 TRS2 = -4.0e-5) .MODEL DESD1MOD D (BV = 13.54 TBV1 = 0 TBV2 = 0 RS = 45.5 TRS1 = 0 TRS2 = 0) .MODEL DESD2MOD D (BV = 11.46 TBV1 = -7.576e-4 TBV2 = -3.0e-6 RS = 0 TRS1 = 0 TRS2 = 0) .MODEL DPLCAPMOD D (CJO = 0.591e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.94 KP = 139.2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 1.07e-3 TC2 = -3.03e-7) .MODEL RDSMOD RES (TC1 = 5.38e-3 TC2 = 1.64e-5) .MODEL RSLVCMOD RES (TC1 = 1.75e-3 TC2 = 3.90e-6) .MODEL RVTOMOD RES (TC1 = -2.15e-3 TC2 = -5.43e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF = -1.5) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF = -4.05) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.2 VOFF = 2.8) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.8 VOFF = -2.2) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records 1991.
ESG +
rev 6/2/93
DPLCAP 10 RSCL2
5
DRAIN 2 LDRAIN RSCL1 + 51 DBREAK 11 EBREAK RDRAIN + 17 18 DBODY
6 8 VTO + 16
5 51
ESCL 50
21 MOS1 MOS2
GATE 1 EVTO 20 + 18 8 LGATE RGATE 9 DESD1 91 DESD2 6
RIN
CIN 8 RSOURCE 7 LSOURCE 3 SOURCE
S1A 12 S1B CA EGS 13 8 14 13
S2A 15 S2B 13 + 6 8 EDS CB + 5 8 14 IT RBREAK 17 18 RVTO 19 VBAT +
-
-
(c)2004 Fairchild Semiconductor Corporation
RFP30N06LE, RF1S30N06LESM Rev. B1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM FACT Quiet SeriesTM ActiveArrayTM FAST BottomlessTM FASTrTM CoolFETTM FRFETTM CROSSVOLTTM GlobalOptoisolatorTM DOMETM GTOTM EcoSPARKTM HiSeCTM E2CMOSTM I2CTM TM EnSigna ImpliedDisconnectTM FACTTM ISOPLANARTM Across the board. Around the world.TM The Power FranchiseTM Programmable Active DroopTM
DISCLAIMER
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Power247TM PowerTrench QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM SILENT SWITCHER SMART STARTTM SPMTM StealthTM SuperFETTM
SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogic TINYOPTOTM TruTranslationTM UHCTM UltraFET VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I6

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